HD64F3028F25 Datasheet, PDF (646/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

4. As in on-board programming mode, care is required when applying and releasing FWE
to prevent erroneous programming or erasing. To prevent erroneous programming and
erasing due to program runaway during FWE application, in particular, the watchdog
timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while
the emulation function is being used.
5. When the emulation function is used, NMI input is prohibited when the P bit or E bit is
set to 1 in FLMCR1, in the same way as with normal programming and erasing.
The P and E bits are cleared by a reset (including a watchdog timer reset), in standby
mode, when a high level is not being input to the FWE pin, or when the SWE bit in
FLMCR1 is 0 while a high level is being input to the FWE pin.
18.9 NMI Input Disabling Conditions
All interrupts, including NMI input, should be disabled while flash memory is being programmed
or erased (while the P bit or E bit is set in FLMCR1), and while the boot program is executing in
boot mode*¹, to give priority to the program or erase operation. There are three reasons for this:
1. NMI input during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the NMI exception handling sequence during programming or erasing, the vector would not
be read correctly*², possibly resulting in MCU runaway.
3. If NMI input occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling NMI
input, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests (exception handling and bus
release), including NMI, must therefore be restricted inside and outside the MCU during FWE
application. NMI input is also disabled in the error protection state and while the P or E bit
remains set in FLMCR1 during flash memory emulation in RAM.
Notes: 1. This is the interval until a branch is made to the boot program area in the on-chip RAM
(This branch takes place immediately after transfer of the user program is completed).
Consequently, after the branch to the RAM area, NMI input is enabled except during
programming and erasing. Interrupt requests must therefore be disabled inside and
outside the MCU until the user program has completed initial programming (including
the vector table and the NMI interrupt handling routine).
2. The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P bit or E bit
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
Rev. 2.00, 09/03, page 614 of 890