HD64F3028F25 Datasheet, PDF (41/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Type
System
control
Interrupts
Address
bus
Data bus
Bus
control
Symbol
RES
RESO
FWE
STBY
BREQ
BACK
NMI
IRQ5 to
IRQ0
A23 to A0
D15 to D0
CS7 to CS0
AS
RD
HWR
LWR
WAIT
Pin No.
FP-100B
TFP-100B
63
I/O
Input
10
Output
10
Input
62
Input
59
Input
60
Output
64
Input
17, 16,
90 to 87
97 to 100,
56 to 45,
43 to 36
34 to 23,
21 to 18
2 to 5,
88 to 91
69
Input
Output
Input/
output
Output
Output
70
Output
71
Output
72
Output
58
Input
Name and Function
Reset input: When driven low, this pin resets
the chip
Reset output (mask ROM version): Outputs
the reset signal generated by the watchdog timer
to an external device
Write enable signal (F-ZTAT version): Flash
memory write control signal
Standby: When driven low, this pin forces a
transition to hardware standby mode
Bus request: Used by an external bus master to
request the bus right
Bus request acknowledge: Indicates that the
bus has been granted to an external bus master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Address bus: Outputs address signals
Data bus: Bidirectional data bus
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from the
external address space
High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D15 to D8).
Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D7 to D0).
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
Rev. 2.00, 09/03, page 9 of 890