HD64F3028F25 Datasheet, PDF (507/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

The BRR setting is calculated as follows:
Asynchronous mode:
φ
N=
× 10⁶ – 1
64 × 2^2n–1 × B
Synchronous mode:
φ
N=
× 10⁶ – 1
8 × 2^2n–1 × B
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n
Clock Source
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is calculated as follows:
Error (%) =
φ × 10⁶
– 1 × 100
(N + 1) × B × 64 × 2^2n–1
Rev. 2.00, 09/03, page 475 of 890