HD64F3028F25 Datasheet, PDF (424/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

φ
External clock input
8TCNT input clock
8TCNT
N–1
N
N+1
Figure 10.9 Count Timing for External Clock Input (Both-Edge Detection)
10.4.2 Compare Match Timing
Timer Output Timing: When compare match A or B occurs, the timer output is as specified by
the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Figure 10.10 shows the timing when the output is set to toggle on compare match A.
φ
Compare match A
signal
Timer output
Figure 10.10 Timing of Timer Output
Rev. 2.00, 09/03, page 392 of 890