HD64F3028F25 Datasheet, PDF (240/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the
data transfer activation source. The selectable activation sources differ between normal mode and
block transfer mode.
• Normal mode
Bit 2
DTS2B
0
1
Bit 1
DTS1B
0
1
0
1
Bit 0
DTS0B
0
1
0
1
0
1
0
1
Description
Auto-request (burst mode)
Cannot be used
Auto-request (cycle-steal mode)
Cannot be used
Cannot be used
Cannot be used
Falling edge of DREQ
Low level input at DREQ
(Initial value)
• Block transfer mode
Bit 2 Bit 1 Bit 0
DTS2B DTS1B DTS0B Description
0
0
0
Compare match/input capture A interrupt from 16-bit timer channel 0
(Initial value)
1
Compare match/input capture A interrupt from 16-bit timer channel 1
1
0
Compare match/input capture A interrupt from 16-bit timer channel 2
1
Conversion-end interrupt from A/D converter
1
0
0
Cannot be used
1
Cannot be used
1
0
Falling edge of DREQ
1
Cannot be used
The same internal interrupt can be selected to activate two or more channels. The channels are
activated in a priority order, highest priority first. For the priority order, see section 7.4.9,
Multiple-Channel Operation.
Rev. 2.00, 09/03, page 208 of 890