HD64F3028F25 Datasheet, PDF (563/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Start
Initialization
Start receiving
ORER = 0
No
and PER = 0?
Yes
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag to 0 in SSR
Error handling
No
All data received?
Yes
Clear RE bit to 0
Figure 14.8 Sample Reception Processing Flowchart
The above procedure may include interrupt handling and DMA transfer.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive-data-full interrupt (RXI) will be requested. If an error occurs in reception
and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) will
be requested.
If the RXI interrupt activates the DMAC, the number of bytes designated in the DMAC will be
transferred, skipping receive data in which an error occurred.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
If a parity error occurs during reception and the PER flag is set to 1, the received data is
transferred to RDR, so the erroneous data can be read.
Rev. 2.00, 09/03, page 531 of 890