HD64F3028F25 Datasheet, PDF (334/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Pin
PB4/TP12/
UCAS
PB3/TP11/
TMIO3/
DREQ1/CS4
Pin Functions and Selection Method
Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows.
PB4DDR
0
1
1
NDER12
—
0
1
Pin function
PB4 input
PB4 output
UCAS output^*
TP12 output
Note: * UCAS output depending on bits DRAS2 to DRAS0 in DRCRA and bit
CSEL in DRCRB, and regardless of bits NDER12 and PB4DDR. For
details, see section 6, Bus Controller.
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2
and OS1/0 in 8TCSR3, bits CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit
NDER11 in NDERB, and bit PB3DDR select the pin function as follows.
DRAM interface
settings
(1) in table below
(2) in
table
below
OIS3/2 and
OS1/0
All 0
Not all 0
—
CS4E
0
1
—
—
PB3DDR
NDER11
0
1
—
0
1
—
—
—
1
—
—
—
Pin function
PB3
input
PB3
output
TP11
output
CS4
output
TMIO3
CS4
output output^*3
TMIO3 input^*1
DREQ1 input^*2
Notes: 1. TMIO3 input when CCLR1 = CCLR0 = 1.
2. When an external request is specified as a DMAC activation source,
DREQ1 input regardless of bits OIS3 and OIS2, OS1 and OS0, CCLR1
and CCLR0, CS4E, NDER11, and PB3DDR.
3. CS4 is output as RAS4.
DRAM interface
(1)
settings
(2)
(1)
DRAS2
0
1
DRAS1
0
1
0
1
DRAS0
0
1
0
1
0
1
0
1
Rev. 2.00, 09/03, page 302 of 890