HD64F3028F25 Datasheet, PDF (708/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

φ
NMI
IRQ _E
IRQ _L
t_NMIS t_NMIH
t_NMIS t_NMIH
t_NMIS
IRQ _E: Edge-sensitive IRQ _i
IRQ _L : Level-sensitive IRQ _i (i = 0 to 5)
NMI
t_NMIW
IRQ _j
(j = 0 to 5)
Figure 21.10 Interrupt Input Timing
21.3.3 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 21.11 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 21.12 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 21.13 shows the timing of the external three-state access cycle with one wait state
inserted.
• Bus-release mode timing
Figure 21.14 shows the bus-release mode timing.
Rev. 2.00, 09/03, page 676 of 890