HD64F3028F25 Datasheet, PDF (280/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Table 8.1 Port Functions
Port
Description
Pins
Port 1 • 8-bit I/O port
P17 to P10/
• Can drive LEDs ^{A7 to A0}
Port 2 • 8-bit I/O port
P27 to P20/
• Built-in input pull- ^{A15 to A8}
up transistors
• Can drive LEDs
Port 3 • 8-bit I/O port
P37 to P30/
D15 to D8
Expanded Modes
Mode 1 Mode 2 Mode 3 Mode 4
Mode 5
Address output pins (A7 to A0)
Address output (A7 to
A0) and generic input
DDR = 0:
generic input
DDR = 1:
address output
Address output pins (A15 to A8)
Address output (A15 to
A8) and generic input
DDR = 0:
generic input
DDR = 1:
address output
Data input/output (D15 to D8)
Single-Chip Modes
Mode 6
Mode 7
Generic input/output
Generic input/output
Generic input/output
Port 4 • 8-bit I/O port
P47 to P40/
• Built-in input pull- ^{D7 to D0}
up transistors
Data input/output (D7 to D0) and 8-bit generic input/output
8-bit bus mode: generic input/output
16-bit bus mode: data input/output
Generic input/output
Port 5 • 4-bit I/O port
P53 to P50/
• Built-in input pull- ^{A19 to A16}
up transistors
• Can drive LEDs
Address output (A19 to A16)
Address output (A19 to
A16) and 4-bit
generic input
Generic input/output
DDR = 0: generic input
DDR = 1: address output
Port 6 • 8-bit I/O port
Port 7 • 8-bit I/O port
P67/φ
P66/LWR
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
P77/AN7/DA1
P76/AN6/DA0
P75 to P70/
AN5 to AN0
Clock output (φ) and generic input
Bus control signal output (LWR, HWR, RD, AS)
Generic input/output
Bus control signal input/output (BACK, BREQ, WAIT) and 3-bit generic input/output
Analog input (AN7, AN6) to A/D converter, analog output (DA1, DA0) from D/A converter, and generic
input
Analog input (AN5 to AN0) to A/D converter, and generic input
Port 8 • 5-bit I/O port
• P82 to P80 have
Schmitt inputs
P84/CS0
DDR = 0: generic input
DDR = 1 (reset value): CS0 output
DDR = 0 (reset value):
generic input
DDR = 1: CS0 output
P83/IRQ3/
IRQ3 input, CS1 output, external trigger input (ADTRG) to A/D converter,
CS1/ADTRG and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS1 output
P82/IRQ2/CS2 IRQ2 and IRQ1 input, CS2 and CS3 output, and generic input^*
P81/IRQ1/CS3 DDR = 0 (reset value): generic input
DDR = 1: CS2 and CS3 output
P80/IRQ0/
RFSH
IRQ0 input, RFSH output, and generic input/output
Note: * P81 can be used as an output port by making a setting in DRCRA.
Generic input/output
IRQ3 input, external
trigger input (ADTRG) to
A/D converter, and
generic input/output
IRQ2 and IRQ1 input and
generic input/output
IRQ0 input and generic
input/output
Rev. 2.00, 09/03, page 248 of 890