HD64F3028F25 Datasheet, PDF (207/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

T1
T2
T3
φ
Address bus
Internal write signal
RTCNT address
Counter clear signal
RTCNT
N
H'00
Figure 6.39 Contention between RTCNT Write and Clear
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T₃ state
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 6.40.
T1
T2
T3
φ
Address bus
RTCNT address
Internal write signal
RTCNT input clock
RTCNT
N
M
Counter write data
Figure 6.40 Contention between RTCNT Write and Increment
Rev. 2.00, 09/03, page 175 of 890