HD64F3028F25 Datasheet, PDF (192/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as
accesses are to the same row address, burst operation can be continued without interruption even if
accesses are not consecutive by holding the RAS signal low.
• RAS Down Mode
To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM
space is interrupted and another space is accessed, the RAS signal is held low during the
access to the other space, and burst access is performed if the row address of the next DRAM
space access is the same as the row address of the previous DRAM space access. Figure 6.23
shows an example of the timing in RAS down mode.
DRAM access
External space
access
DRAM access
Tp
Tr
Tc1
Tc2
T1
T2
Tc1
Tc2
φ
A23 to A0
AS
CSn (RAS)
PB₄/PB₅
(UCAS/LCAS)
D15 to D0
Note: n = 2 to 5
Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0)
When RAS down mode is selected, the conditions for an asserted RASn signal to return to the
high level are as shown below. The timing in these cases is shown in figure 6.24.
 When DRAM space with a different row address is accessed
 Immediately before a CAS-before-RAS refresh cycle
 When the BE bit or RDM bit is cleared to 0 in DRCRA
 Immediately before release of the external bus
Rev. 2.00, 09/03, page 160 of 890