HD64F3028F25 Datasheet, PDF (720/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

21.3.8 DMAC Timing
DMAC timing is shown as follows.
• DMAC TEND output timing for 2 state access
Figure 21.25 shows the DMAC TEND output timing for 2-state access.
• DMAC TEND output timing for 3 state access
Figure 21.26 shows the DMAC TEND output timing for 3-state access.
• DMAC DREQ input timing
Figure 21.27 shows DMAC DREQ input timing.
φ
TEND
T₁
t_TED1
T₂
t_TED2
Figure 21.25 DMAC TEND Output Timing for 2-State Access
φ
TEND
T₁
T₂
t_TED1
T₃
t_TED2
Figure 21.26 DMAC TEND Output Timing for 3-State Access
φ
DREQ
t_DRQS t_DRQH
Figure 21.27 DMAC DREQ Input Timing
Rev. 2.00, 09/03, page 688 of 890