HD64F3028F25 Datasheet, PDF (156/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If
areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1.
Bit 0
RFSHE
0
1
Description
RFSH pin refresh signal output disabled
(RFSH pin can be used as input/output port)
RFSH pin refresh signal output enabled
(Initial value)
6.2.8 DRAM Control Register B (DRCRB)
Bit
7
6
5
4
3
MXC1 MXC0 CSEL RCYCE —
Initial value 0
0
0
Read/Write R/W
R/W
R/W
0
1
R/W
—
2
TPC
0
R/W
1
RCW
0
R/W
0
RLW
0
R/W
DRCRB is an 8-bit readable/writable register that selects the number of address multiplex column
address bits for the DRAM interface, the column address strobe output pin, enabling or disabling
of refresh cycle insertion, the number of precharge cycles, enabling or disabling of wait state
insertion between RAS and CAS, and enabling or disabling of wait state insertion in refresh
cycles.
DRCRB is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
The settings in this register are invalid when bits DRAS2 to DRAS0 in DRCRA are all 0.
Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row
address/column address multiplexing method used on the DRAM interface. In burst operation, the
row address used for comparison is determined by the setting of these bits and the bus width of the
relevant area set in ABWCR.
Rev. 2.00, 09/03, page 124 of 890