HD64F3028F25 Datasheet, PDF (818/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

DTCR0B—Data Transfer Control Register 0B (cont)
H'FFF2F
• Full address mode
Bit
7
6
DTME
—
Initial value
0
0
Read/Write R/W
R/W
5
DAID
0
R/W
4
DAIDE
0
R/W
3
TMS
0
R/W
2
DTS2B
0
R/W
1
DTS1B
0
R/W
0
DTS0B
0
R/W
DMAC0
Data transfer master enable
0 Data transfer is disabled
1 Data transfer is enabled
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
Data Transfer Activation Source
DTS2B DTS1B DTS0B
Normal Mode
Block Transfer Mode
Auto-request
0 (burst mode)
0
Not available
0
1
Compare match/input
capture A interrupt from
16-bit timer channel 0
Compare match/input
capture A interrupt from
16-bit timer channel 1
Auto-request
0 (cycle-steal mode)
1
Compare match/input
capture A interrupt from
16-bit timer channel 2
1 Not available
A/D converter conversion
end interrupt
1
0 Not available
0
1 Not available
Not available
Not available
1
0
Falling edge input of
DREQ
Falling edge input of
DREQ
1 Low level input at DREQ Not available
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5 Bit 4
DAID DAIDE
Increment/Decrement Enable
0 MARB is held fixed
0
1 Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
0 MARB is held fixed
1
1 Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
Rev. 2.00, 09/03, page 786 of 890