HD64F3028F25 Datasheet, PDF (202/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

• Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the
corresponding address map. The DRAMs used in this example are of the 9-bit row address ×
10-bit column address type. In this example, upper address decoding allows multiple DRAMs
to be connected to a single area. The RFSH pin is used in this case, since both DRAMs must
be refreshed simultaneously. However, note that RAS down mode cannot be used in this
interconnection example.
H8/3028 Group chip
CS₂ (RAS₂)
PB₄ (UCAS)
PB₅ (LCAS)
RD (WE)
RFSH
A₁₉
A₉-A₁
D₁₅-D₀
2-CAS 4-Mbit DRAM
9-bit row address × 9-bit column address
× 16-bit organization
RAS
UCAS
LCAS
WE
No.1
A₈-A₀
D₁₅-D_{0 OE}
RAS
UCAS
LCAS
WE
No.2
A₈-A₀
D₁₅-D₀
OE
Area 2
(a) Interconnections (example)
PB₄
(UCAS)
PB₅
(LCAS)
15
H'400000
87
0
DRAM (No.1)
H'47FFFE
H'480000
DRAM (No.2)
H'4FFFFE
H'500000
CS₂ (RAS₂)
Not used
H'5FFFFE
16-Mbyte mode
(b) Address map
Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with × 16-Bit
Organization
Rev. 2.00, 09/03, page 170 of 890