HD64F3028F25 Datasheet, PDF (825/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TMDR—Timer Mode Register
H'FFF62
16-bit timer (all channels)
Bit 7
6
5
4
— MDF FDIR —
Initial value 1
0
0
1
Read/Write —
R/W R/W
—
3
2
1
0
— PWM2 PWM1 PWM0
1
0
0
0
—
R/W R/W R/W
PWM mode 0
0 Channel 0 operates normally (Initial value)
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally (Initial value)
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in PWM mode
Flag direction
0 ^{OVF is set to 1 in TISRC when TCNT2}
overflows or underflows (Initial value)
OVF is set to 1 in TISRC when TCNT2
1 _overflows
Phase counting mode flag
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in phase counting mode
Rev. 2.00, 09/03, page 793 of 890