HD64F3028F25 Datasheet, PDF (13/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Item
13.2.8 Bit Rate
Register (BRR)
Table 13.3 Examples
of Bit Rates and BRR
Settings in
Asynchronous Mode
Page
473
Revision (See Manual for Details)
Table amended
Bit
Rate
(bit/s) n
110 3
150 3
300 2
600 2
1200 1
2400 1
4800 0
9600 0
φ (MHz)
25
Error
N
(%)
110 –0.02
80
0.47
162 –0.15
80
0.47
162 –0.15
80
0.47
162 –0.15
80
0.47
15.6 Usage Notes
556
Table 15.5 Analog
Input Pin Ratings
18.12.1 Block Diagram 622
Figure 18.19 ROM
Block Diagram
19.2.1 Connecting a 626
Crystal Resonator
Table 19.1(1)
Damping Resistance
Value
19.2.2 External Clock 629
Input
Table 19.3 Clock
Timing
Note amended
Note: * When conversion time = 134 states, VCC = 3.0 V to 3.6 V,
and φ ≤ 13 MHz. For details see section 21, Electrical
Characteristics.
Figure amended
H'5FFFE
Even addresses
Note amended
Note:
A crystal resonator between 2 MHz and 25 MHz can be
used. If the chip is to be operated at less than 2 MHz, the
on-chip frequency divider should be used. (A crystal
resonator of less than 2 MHz cannot be used.)
Table amended
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
VCC = 3.0 V to 3.6 V
Symbol Min Max Unit
tEXL
0.3
0.7
tcyc
60
—
ns
tEXH
0.3
0.7
tcyc
60
—
ns
tEXr
—
5
ns
tEXf
—
5
ns
tCL
0.4
0.6
tcyc
80
—
ns
tCH
0.4
0.6
tcyc
80
—
ns
tDEXT^*
500
—
µs
Test Conditions
φ ≥ 5 MHz
φ < 5 MHz
φ ≥ 5 MHz
φ < 5 MHz
Figure 19.6
Figure
19.6
φ ≥ 5 MHz
φ < 5 MHz
Figure
21.11
φ ≥ 5 MHz
φ < 5 MHz
Figure 19.7
Rev. 2.00, 09/03, page xi of xxx