HD64F3028F25 Datasheet, PDF (201/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

• Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit
organization, and the corresponding address map. The DRAMs used in this example are of the
11-bit row address × 10-bit column address type. The CS₂ pin is used as the common RAS
output pin for areas 2 and 3. When the DRAM address space spans a number of contiguous
areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single CS
pin to be used as the common RAS output pin for a number of areas, and makes it possible to
directly connect large-capacity DRAM with address space that spans a maximum of four areas.
Any unused CS pins (in this example, the CS₃ pin) can be used as input/output ports.
H8/3028 Group chip
CS₂ (RAS₂)
PB₄ (UCAS)
PB₅ (LCAS)
RD (WE)
A₂₁, A₁₀-A₁
D₁₅-D₈
D₇-D₀
2-CAS 16-Mbit DRAM
11-bit row address × 10-bit column address
× 8-bit organization
RAS
CAS
WE
A₁₀-A₀
No.1
D₇-D₀
OE
RAS
CAS
WE
No.2
A₁₀-A₀
D₇-D₀
OE
Area 2
Area 3
Area 4
Area 5
(a) Interconnections (example)
H'400000
PB₄
(UCAS)
15
PB₅
(LCAS)
87
0
H'5FFFFE
H'600000
DRAM
(No.1)
DRAM
(No.2)
CS₂(RAS₂)
H'7FFFFE
H'800000
Normal
CS₄
H'9FFFFE
H'A00000
Normal
CS₅
H'BFFFFE
16-Mbyte mode
(b) Address map
Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with × 8-Bit
Organization
Rev. 2.00, 09/03, page 169 of 890