HD64F3028F25 Datasheet, PDF (639/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Start
*1
Set SWE bit in FLMCR1
Wait (t_sswe) µs
Perform erasing in block units.
*5
n=1
Set EBR1 or EBR2
*3 *4
Enable WDT
Set ESU bit in FLMCR1
Wait (t_sesu) µs
Set E bit in FLMCR1
Wait (t_se) ms
Clear E bit in FLMCR1
Wait (t_ce) µs
Clear ESU bit in FLMCR1
Wait (t_cesu) µs
Disable WDT
*5
Start of erase
*5
End of erase
*5
*5
Set EV bit in FLMCR1
Wait (t_sev) µs
*5
Set block start address as verify address
n←n+1
H'FF dummy write to verify address
Wait (t_sevr) µs
*5
Increment
address
No
Read verify data
Verify data = all 1s?
Yes
Last address of block?
Yes
Clear EV bit in FLMCR1
*2
No
Wait (t_cev) µs
*5
Clear SWE bit in FLMCR1
Wait (t_cswe) µs
*5
End of erasing
Clear EV bit in FLMCR1
Re-erase
Wait (t_cev) µs
*5
n ≥ N?
Yes
Clear SWE bit in FLMCR1
*5
No
Wait (t_cswe) µs
*5
Erase failure
Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Verify data is read in 16-bit (word) units.
3. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously.
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
5. The wait times and the value of N are shown in section 21.2.6, Flash Memory Characteristics.
Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)
Rev. 2.00, 09/03, page 607 of 890