HD64F3028F25 Datasheet, PDF (717/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

φ
CS₅ to CS₂
(RAS₅ to
RAS₂)
UCAS,
LCAS
t_CSR2
RD (WE)
(high)
RFSH
t_CSR2
Figure 21.19 DRAM Bus Timing (Self-Refresh)
21.3.5 TPC and I/O Port Timing
Figure 21.20 shows the TPC and I/O port input/output timing.
φ
Port 1 to
B (read)
Port 1 to
6, 8 to B
(write)
T₁
T₂
T₃
t_PRS
t_PRH
t_PWD
Figure 21.20 TPC and I/O Port Input/Output Timing
Rev. 2.00, 09/03, page 685 of 890