HD64F3028F25 Datasheet, PDF (21/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5.1.4 Register Configuration ......................................................................................... 83
5.2 Register Descriptions......................................................................................................... 83
5.2.1 System Control Register (SYSCR) ...................................................................... 83
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 84
5.2.3 IRQ Status Register (ISR) .................................................................................... 90
5.2.4 IRQ Enable Register (IER)................................................................................... 91
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 92
5.3 Interrupt Sources ............................................................................................................... 93
5.3.1 External Interrupts................................................................................................ 93
5.3.2 Internal Interrupts ................................................................................................. 94
5.3.3 Interrupt Vector Table.......................................................................................... 94
5.4 Interrupt Operation ............................................................................................................ 98
5.4.1 Interrupt Handling Process................................................................................... 98
5.4.2 Interrupt Sequence................................................................................................ 103
5.4.3 Interrupt Response Time ...................................................................................... 104
5.5 Usage Notes....................................................................................................................... 105
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 105
5.5.2 Instructions that Inhibit Interrupts ........................................................................ 106
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 106
Section 6 Bus Controller.................................................................................................... 107
6.1 Overview ........................................................................................................................... 107
6.1.1 Features ................................................................................................................ 107
6.1.2 Block Diagram ..................................................................................................... 109
6.1.3 Pin Configuration ................................................................................................. 110
6.1.4 Register Configuration ......................................................................................... 111
6.2 Register Descriptions......................................................................................................... 112
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 112
6.2.2 Access State Control Register (ASTCR).............................................................. 113
6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 113
6.2.4 Bus Release Control Register (BRCR)................................................................. 117
6.2.5 Bus Control Register (BCR)................................................................................. 118
6.2.6 Chip Select Control Register (CSCR) .................................................................. 121
6.2.7 DRAM Control Register A (DRCRA) ................................................................. 122
6.2.8 DRAM Control Register B (DRCRB).................................................................. 124
6.2.9 Refresh Timer Control/Status Register (RTMCSR)............................................. 126
6.2.10 Refresh Timer Counter (RTCNT) ........................................................................ 128
6.2.11 Refresh Time Constant Register (RTCOR).......................................................... 128
6.2.12 Address Control Register (ADRCR) .................................................................... 129
6.3 Operation........................................................................................................................... 130
6.3.1 Area Division ....................................................................................................... 130
6.3.2 Bus Specifications ................................................................................................ 132
6.3.3 Memory Interfaces ............................................................................................... 133
Rev. 2.00, 09/03, page xix of xxx