HD64F3028F25 Datasheet, PDF (477/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
12.3.1 Watchdog Timer Operation
Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow by rewriting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash, etc., the H8/3028 Group is internally reset for a duration of 518
states.
It is possible to output the reset signal generated by the WDT to an external device from the RESO
pin and thereby reset the external system. The external reset signal is output for a duration of 132
states. External output of the reset signal is enabled or disabled using the RSTOE bit in RSTCSR.
Note, however, that the flash memory version is not equipped with a RESO pin.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority.
H'FF
TCNT count
value
H'00
Internal
reset signal
Start
WDT overflow
TME set to 1
OVF = 1
H'00 written
in TCNT
Reset
H'00 written
in TCNT
RESO
518 states
132 states
Figure 12.4 Operation in Watchdog Timer Mode
Rev. 2.00, 09/03, page 445 of 890