HD64F3028F25 Datasheet, PDF (800/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

DRCRA—DRAM Control Register A
H'EE026
DRAM interface
Bit
7
6
5
4
DRAS2 DRAS1 DRAS0 —
Initial value
0
0
0
1
Read/Write R/W R/W R/W —
3
2
1
0
BE RDM SRFMD RFSHE
0
0
0
0
R/W R/W R/W R/W
Refresh pin enable
0 RFSH pin refresh signal output is disabled
1 RFSH pin refresh signal output is enabled
Self-refresh mode
0 DRAM self-refreshing is disabled in software standby mode
1 DRAM self-refreshing is enabled in software standby mode
RAS down mode
0 DRAM interface: RAS up mode selected
1 DRAM interface: RAS down mode selected
Burst access enable
0 Burst disabled (always full access)
1 DRAM space access performed in fast page mode
DRAM area select
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
0
Normal
Normal
Normal
Normal
1
Normal
Normal
Normal DRAM space
(CS₂)
1
0
Normal Normal DRAM space DRAM space
(CS₃)
(CS₂)
1
Normal Normal
DRAM space(CS₂)*
1
0
0
Normal DRAM space DRAM space DRAM space
(CS₄)
(CS₃₎
(CS₂)
1 DRAM space DRAM space DRAM space DRAM space
(CS₅)
(CS₄)
(CS₃)
(CS₂)
1
0
1
DRAM space(CS₄)*
DRAM space(CS₂)*
DRAM space(CS₂)*
Note: * A single CSn pin serves as a common RAS output pin for a number of
areas. Unused CSn pins can be used as input/output ports.
Rev. 2.00, 09/03, page 768 of 890