HD64F3028F25 Datasheet, PDF (266/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
φ
DREQ
End of 1 block transfer
DMAC cycle
CPU cycle
DMAC cycle
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
Rev. 2.00, 09/03, page 234 of 890