HD64F3028F25 Datasheet, PDF (351/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting
Direction
TCLKA pin
TCLKB pin
Down-Counting
↑
High ↓
Low
Low
↑
High ↓
Up-Counting
Low
↑
High ↓
↑
High ↓
Low
In phase counting mode, external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2
and counter clock selection by bits TPSC2 to TPSC0 are invalid, and the above phase counting
mode operations take precedence.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR
0
1
Description
OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
OVF is set to 1 in TISRC when 16TCNT2 overflows
(Initial value)
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Rev. 2.00, 09/03, page 319 of 890