HD64F3028F25 Datasheet, PDF (662/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

V_CC
STBY
V_IH
EXTAL
φ (internal or
external)
RES
t_DEXT
Figure 19.7 External Clock Output Settling Delay Timing
19.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
19.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
19.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
Rev. 2.00, 09/03, page 630 of 890