HD64F3028F25 Datasheet, PDF (116/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
0
UE NMIEG SSOE RAME
1
0
0
1
R/W
R/W
R/W
R/W
RAM enable
Standby timer
select 2 to 0
Software standby
Software standby
output port enable
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE
0
1
Description
UI bit in CCR is used as interrupt mask bit
UI bit in CCR is used as user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG
0
1
Description
Interrupt is requested at falling edge of NMI input
Interrupt is requested at rising edge of NMI input
(Initial value)
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
Rev. 2.00, 09/03, page 84 of 890