HD64F3028F25 Datasheet, PDF (215/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 T1 T2
RD
CSn
φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 Ti T1 T2
RD
CSn
Simultaneous change of RD and CSn
Possibility of mutual overlap
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.47 Example of Idle Cycle Operation (5)
6.9.2 Pin States in Idle Cycle
Table 6.11 shows the pin states in an idle cycle.
Table 6.11 Pin States in Idle Cycle
Pins
Pin State
A23 to A0
D15 to D0
CSn
Next cycle address value
High impedance
High^*
UCAS, LCAS
High
AS
High
RD
High
HWR
High
LWR
High
Note: * Remains low in DRAM space RAS down mode.
Rev. 2.00, 09/03, page 183 of 890