HD64F3028F25 Datasheet, PDF (118/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ₀ interrupt requests.
Bit 7
IPRA7
0
1
Description
IRQ0 interrupt requests have priority level 0 (low priority)
IRQ0 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ₁ interrupt requests.
Bit 6
IPRA6
0
1
Description
IRQ1 interrupt requests have priority level 0 (low priority)
IRQ1 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 5—Priority Level A5 (IPRA5): Selects the priority level of IRQ₂ and IRQ₃ interrupt requests.
Bit 5
IPRA5
0
1
Description
IRQ2 and IRQ3 interrupt requests have priority level 0 (low priority)
IRQ2 and IRQ3 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ₄ and IRQ₅ interrupt requests.
Bit 4
IPRA4
0
1
Description
IRQ4 and IRQ5 interrupt requests have priority level 0 (low priority)
IRQ4 and IRQ5 interrupt requests have priority level 1 (high priority)
(Initial value)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D
converter interrupt requests.
Bit 3
IPRA3
0
1
Description
WDT, DRAM interface, and A/D converter interrupt requests have priority level 0
(low priority)
(Initial value)
WDT, DRAM interface, and A/D converter interrupt requests have priority level 1
(high priority)
Rev. 2.00, 09/03, page 86 of 890