HD64F3028F25 Datasheet, PDF (12/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Item
7.4.10 External Bus
Requests, DRAM
Interface, and DMAC
Figure 7.20 Bus
Timing of DRAM
Interface, and DMAC
Page
236
Revision (See Manual for Details)
Figure amended
DMAC cycle (channel 0)
Refresh
cycle
DMAC cycle (channel 0)
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂
φ
Address
bus
RD
HWR , LWR
7.4.14 DMAC States 240
in Reset State, Standby
Modes, and Sleep
Mode
Figure amended
CPU cycle
DMAC cycle
Sleep mode
DMAC cycle
Figure 7.24 Timing of
Cycle-Steal Transfer in
Sleep Mode
T₂ T_d T₁ T₂ T₁ T₂
T_d T₁ T₂ T₁ T₂
T_d
φ
Address bus
RD
HWR , LWR
7.6.8 Bus Cycle when 245
Transfer is Aborted
Figure 7.27 Bus
Timing at Abort of DMA
Transfer in Cycle-Steal
Mode
Figure amended
CPU cycle
DMAC cycle
CPU cycle
DMAC
cycle
CPU cycle
T₁ T₂ T_d T₁ T₂ T₁ T₂ T₁ T₂ T₃ T_d T_d T₁ T₂
φ
Address bus
RD
12.2.3 Reset Control/ 442
Status Register
(RSTCSR)
Bit 7—Watchdog Timer
Reset (WRST)
HWR, LWR
DTE bit is
cleared
Description amended
At the same time, if the RSTOE bit is set to 1, the reset signal is
output from the RESO pin as low-level output to an external
device, making it possible to reset the entire system.
Rev. 2.00, 09/03, page x of xxx