HD64F3028F25 Datasheet, PDF (166/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3028 Group can output a chip select signal (CS₀ to CS₇) that goes
low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output
timing of a CSn signal.
Output of CS₀ to CS₃: Output of CS₀ to CS₃ is enabled or disabled in the data direction register
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS₀ in the output state and
pins CS₁ to CS₃ in the input state. To output chip select signals CS₁ to CS₃, the corresponding
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS₀ to CS₃ in the input state. To output chip select signals CS₀ to CS₃, the corresponding DDR
bits must be set to 1. For details, see section 8, I/O Ports.
Output of CS₄ to CS₇: Output of CS₄ to CS₇ is enabled or disabled in the chip select control
register (CSCR). A reset leaves pins CS₄ to CS₇ in the input state. To output chip select signals
CS₄ to CS₇, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
φ
Address
External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS₀ to CS₇ remain
high. The CS_n signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
Rev. 2.00, 09/03, page 134 of 890