HD64F3028F25 Datasheet, PDF (193/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

DRAM access cycle
φ
RASn
φ
(a) Access to DRAM space with a different row address
CBR refresh cycle
RASn
φ
(b) CAS-before-RAS refresh cycle
DRCRA write cycle
RASn
(c) BE bit or RDM bit cleared to 0 in DRCRA
External bus released
φ
RASn
High-impedance
(d) External bus released
Note: n = 2 to 5
Figure 6.24 RASn Negation Timing when RAS Down Mode is Selected
Rev. 2.00, 09/03, page 161 of 890