HD64F3028F25 Datasheet, PDF (836/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
H'FFF80
H'FFF81
8-bit timer channel 0
8-bit timer channel 1
Bit
7
6
CMIEB CMIEA
Initial value
0
0
Read/Write R/W
R/W
5
4
3
2
OVIE CCLR1 CCLR0 CKS2
0
0
0
0
R/W
R/W
R/W
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select 2 to 0
0 Clock input is disabled
0
1
Internal clock, counted on rising
edge of φ/8
0
0 Internal clock, counted on rising
1
edge of φ/64
1 ^{Internal clock, counted on rising}
edge of φ/8192
Channel 0:
Count on TCNT1 overflow signal*
Channel 1:
0 _{Count on TCNT0 compare match}
0
A*
1
1 External clock, counted on falling edge
0 External clock, counted on rising edge
1
External clock, counted on both
1 _{rising and falling edges}
Notes: * If the clock input of channel 0 is the TCNT1
overflow signal and that of channel 1 is the
TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
Counter clear 1 and 0
0 Clearing is disabled
0
1 Cleared by compare match A
0 Cleared by compare match B/input capture B
1
1 Cleared by input capture B
Timer overflow interrupt enable
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0 CMIA interrupt requested by CMFA is disabled
1 CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0 CMIB interrupt requested by CMFB is disabled
1 CMIB interrupt requested by CMFB is enabled
Rev. 2.00, 09/03, page 804 of 890