 English |
|
|
|
|
|
|
|
| HD64F3028F25 Datasheet, PDF (713/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series | |||
| |||
| ◁ |
T1
T2
Ï
tAD
A23 to A3
CSn
A2 to A0
tASD
tACC4
AS
tAS1
tASD
tACC4
RD
D15 to D0
tAS1
tACC2
T3
T1
T2
tAD
tSD tAH
tASD
tAS1
tRDS
tACC2
T3
tSD
tAH
tRDS
tRSD
tRDH*
Note: * Specification from the earliest negation timing of A23 to A0, CSn, and RD.
Figure 21.15 Burst ROM Access Timing: Three-State Access
Ï
BREQ
BACK
A23 to A0,
AS, RD,
HWR, LWR
tBRQS
tBRQS
tBACD1
tBZD
Figure 21.16 Bus-Release Mode Timing
tBACD2
tBZD
Rev. 2.00, 09/03, page 681 of 890
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese