HD64F3028F25 Datasheet, PDF (553/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

• If a parity error is detected during reception, a low error signal level is output for a1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
14.3.2 Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to V_CC with a resistor.
When the smart card uses the clock generated on the smart card interface, the SCK pin output is
input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is
unnecessary.
The reset signal should be output from one of the H8/3028 Group’s generic ports.
In addition to these pin connections, power and ground connections will normally also be
necessary.
TxD
RxD
SCK
H8/3028 Group
chip
Px (port)
Card-processing device
V_CC
Data line
Clock line
Reset line
I/O
CLK
RST
Smart card
Figure 14.2 Smart Card Interface Connection Diagram
Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a
smart card.
Rev. 2.00, 09/03, page 521 of 890