HD64F3028F25 Datasheet, PDF (152/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access (burst access on match of address bits above A3)
(Initial value)
Max. 8 words in burst access (burst access on match of address bits above A4)
Bit 2—Expansion Memory Map Control (EMC): Selects either of the two memory maps.
Bit 2
EMC
0
1
Description
Selects the memory map shown in figure 3.2: see section 3.6, Memory Map in
Each Operating Mode
Selects the memory map shown in figure 3.1: see section 3.6, Memory Map in
Each Operating Mode
(Initial value)
When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer
to appendix B.2, Address (when EMC = 0).
This bit is invalid in mode 6. In mode 6 and when the RDEA bit is 0, EMC must not be cleared to
0.
Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit
is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7.
When the EMC bit is 0, RDEA must not be cleared to 0.
Bit 1
RDEA
0
1
Description
Area divisions are as follows: Area 0: 2 Mbytes
Area 1: 2 Mbytes
Area 2: 8 Mbytes
Area 3: 2 Mbytes
Areas 0 to 7 are the same size (2 Mbytes)
Area 4: 1.93 Mbytes
Area 5: 4 kbytes
Area 6: 23.75 kbytes
Area 7: 22 bytes
(Initial value)
Rev. 2.00, 09/03, page 120 of 890