HD64F3028F25 Datasheet, PDF (843/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TCSR2—Timer Control/Status Register 2
TCSR3—Timer Control/Status Register 3
H'FFF92
H'FFF93
8-bit timer channel 2
8-bit timer channel 3
TCSR2
Bit
7
6
5
4
CMFB CMFA OVF
—
Initial value
0
0
0
1
Read/Write R/(W)* R/(W)* R/(W)* —
TCSR3
Bit
7
6
5
4
CMFB CMFA OVF
ICE
Initial value
0
0
0
0
Read/Write R/(W)* R/(W)* R/(W)* R/W
3
OIS3
0
R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
0
OS0
0
R/W
Output select A1 and A0
Bit 1 Bit 0
OS1 OS0
Description
0 No change at compare match A
0
1 0 output at compare match A
0 1 output at compare match A
1
1 Output toggles at compare match A
Output/input capture edge select B3 and B2
ICE in Bit 3 Bit 2
TCSR3 _{OIS3 OIS2}
Description
0 No change at compare match B
0
1 0 output at compare match B
0
0 1 output at compare match B
1
1 Output toggles at compare match B
0 TCORB input capture on rising edge
0
1 TCORB input capture on falling edge
1
1
0 ^{TCORB input capture on both rising}
and falling edges
Input capture enable (TCSR3 only)
0 TCORB is a compare match register
1 TCORB is an input capture register
Timer overflow flag
0 ^{[Clearing condition]}
Read OVF when OVF = 1, then write 0 in OVF.
1
[Setting condition]
TCNT overflows from H'FF to H'00.
Compare match/input capture flag A
[Clearing condition]
0 _{Read CMFA when CMFA = 1, then write 0 in CMFA.}
1
[Setting condition]
TCNT = TCORA
Compare match/input capture flag B
0
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
1
• TCNT = TCORB
• The TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Rev. 2.00, 09/03, page 811 of 890