HD64F3028F25 Datasheet, PDF (579/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

15.2.3 A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGE
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
0
Read/Write
R/W
—
—
—
—
—
—
R/W
Reserved bits
Trigger enable
Enables or disables starting of A/D conversion
by an external trigger or 8-bit timer compare match
ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by
external trigger input or an 8-bit timer compare match signal. ADCR is initialized to H'7F by a
reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external
trigger or 8-bit timer compare match.
Bit 7
TRGE
0
1
Description
Starting of A/D conversion by an external trigger or 8-bit timer compare match is
disabled
(Initial value)
A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or
by an 8-bit timer compare match
External trigger pin and 8-bit timer selection are performed by the 8-bit timer. For details, see
section 10, 8-Bit Timers.
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 1.
Bit 0—Reserved: This bit can be read or written, but must not be set to 1.
Rev. 2.00, 09/03, page 547 of 890