HD64F3028F25 Datasheet, PDF (211/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

6.8.2 Basic Timing
The number of states in the initial cycle (full access) and a burst cycle of the burst ROM interface
is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait states
can also be inserted in the initial cycle. Wait states cannot be inserted in a burst cycle.
Burst access of up to four words is performed when the BRSTS0 bit is cleared to 0 in BCR, and
burst access of up to eight words when the BRSTS0 bit is set to 1. The number of burst access
states is two when the BRSTS1 bit is cleared to 0, and three when the BRSTS1 bit is set to 1.
The basic access timing for burst ROM space is shown in figure 6.42.
Full access
Burst access
T1
T2
T3
T1
T2
T1
T2
φ
Address bus
CS0
AS
RD
Only lower address changes
Data bus
Read data
Read data
Read data
Figure 6.42 Example of Burst ROM Access Timing
6.8.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface.
Wait states cannot be inserted in a burst cycle.
Rev. 2.00, 09/03, page 179 of 890