HD64F3028F25 Datasheet, PDF (115/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

5.1.3 Pin Configuration
Table 5.1 lists the interrupt pins.
Table 5.1 Interrupt Pins
Name
Abbreviation I/O Function
Nonmaskable interrupt
NMI
Input Nonmaskable interrupt^*, rising edge or
falling edge selectable
External interrupt request 5 to 0 IRQ5 to IRQ0 Input Maskable interrupts, falling edge or level
sensing selectable
Note: * NMI input is sometimes disabled. For details see section 18.9, NMI Input Disabling
Conditions.
5.1.4 Register Configuration
Table 5.2 lists the registers of the interrupt controller.
Table 5.2 Interrupt Controller Registers
Address^*1 Name
Abbreviation
H'EE012
System control register
SYSCR
H'EE014
IRQ sense control register
ISCR
H'EE015
IRQ enable register
IER
H'EE016
IRQ status register
ISR
H'EE018
Interrupt priority register A
IPRA
H'EE019
Interrupt priority register B
IPRB
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written, to clear flags.
R/W
R/W
R/W
R/W
R/(W)^*2
R/W
R/W
Initial Value
H'09
H'00
H'00
H'00
H'00
H'00
5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 2.00, 09/03, page 83 of 890