HD64F3028F25 Datasheet, PDF (452/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered
by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4
and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits
7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Address H'FFFA4
Bit
Initial value
Read/Write
7
6
5
4
3
NDR15 NDR14 NDR13 NDR12 —
0
0
0
0
1
R/W
R/W R/W
R/W
—
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Address H'FFFA6
2
1
0
—
—
—
1
1
1
—
—
—
Reserved bits
Bit
7
6
5
4
3
2
1
0
—
—
—
— NDR11 NDR10 NDR9 NDR8
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W R/W
R/W R/W
Reserved bits
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Rev. 2.00, 09/03, page 420 of 890