HD64F3028F25 Datasheet, PDF (113/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted*; either the rising or falling edge can be
selected. For each of IRQ₀ to IRQ₅, sensing of the falling edge or level sensing can be selected
independently.
Note: * In the flash memory, NMI input is sometimes disabled. For details see 18.9, NMI Input
Disable Conditions.
Rev. 2.00, 09/03, page 81 of 890