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HD64F3028F25 Datasheet, PDF (9/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
Main Revisions and Additions in this Edition
Item
1.2 Block Diagram
Figure 1.1 Block
Diagram
1.3.2 Pin Functions
Table 1.2 Pin
Functions
Page
6
Revision (See Manual for Details)
Figure amended
MD 2
MD 1
MD 0
EXTAL
XTAL
STBY
RES
RESO/FWE*
NMI
φ/P67
LWR/P66
HWR/P65
RD/P64
AS/P63
BACK/P62
BREQ/P61
WAIT/P60
Interrupt controller
ROM
(mask ROM or
flash memory)
9
Table amended
System RES 63
control
Input
Reset input: When driven low,
this pin resets the chip
RESO 10
Output
Reset output (mask ROM
version): Outputs the reset signal
generated by the watchdog timer
to an external device
FWE 10
Input
Write enable signal (F-ZTAT
version): Flash memory write
control signal
7.4.8 DMAC Bus
Cycle
Figure 7.13 DMA
Transfer Bus Timing
(Example)
229
Figure amended
CPU cycle
DMAC cycle (1 word transfer)
CPU cycle
φ
Address
bus
RD
T1 T2 T1 T2 Td T1 T2 T1 T2 T3 T1 T2 T3 T1 T2 T1 T2
Source
address
Destination address
HWR
LWR
Rev. 2.00, 09/03, page vii of xxx