HD64F3028F25 Datasheet, PDF (151/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
0
1
Description
No idle cycle inserted in case of consecutive external read cycles for different
areas
Idle cycle inserted in case of consecutive external read cycles for different
areas
(Initial value)
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
0
1
Description
No idle cycle inserted in case of consecutive external read and write cycles
Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
Bit 5—Burst ROM Enable (BROME): Selects whether area 0 is a burst ROM interface area.
Bit 5
BROME
0
1
Description
Area 0 is a basic bus interface area
Area 0 is a burst ROM interface area
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst
ROM interface.
Bit 4
BRSTS1
0
1
Description
Burst access cycle comprises 2 states
Burst access cycle comprises 3 states
(Initial value)
Rev. 2.00, 09/03, page 119 of 890