HD64F3028F25 Datasheet, PDF (707/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

21.3.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 21.8 shows the reset input timing.
• Reset output timing*
Figure 21.9 shows the reset output timing.
• Interrupt input timing
Figure 21.10 shows the interrupt input timing for NMI and IRQ₅ to IRQ₀.
φ
RES
FWE
MD₂ to MD₀
t_RESS
t_MDS
t_SR
t_RESS
t_SF
t_RESW
Figure 21.8 Reset Input Timing
φ
RESO
t_RESD
t_RESD
t_RESOW
Figure 21.9 Reset Output Timing*
Note: * This function is used only in mask ROM models, and is not provided in flash memory
models.
Rev. 2.00, 09/03, page 675 of 890