HD64F3028F25 Datasheet, PDF (841/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TCNT—Timer Counter
H'FFF8D (read),
H'FFF8C (write)
WDT
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Count value
RSTCSR—Reset Control/Status Register
H'FFF8F (read),
H'FFF8E (write)
Bit
7
6
5
4
3
2
WRST RSTOE
—
—
—
—
Initial value
0
0
1
1
1
1
Read/Write R/(W)*
R/W
—
—
—
—
0
0
R/W
R/W
WDT
1
0
—
—
1
1
—
—
Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
Watchdog timer reset
[Clearing conditions]
0 Reset signal at RES pin
Read WRST when WRST = 1, then write 0 in WRST
1 ^{[Setting condition]}
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7, to clear the flag.
Rev. 2.00, 09/03, page 809 of 890