HD64F3028F25 Datasheet, PDF (171/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Table 6.4 Data Buses Used and Valid Strobes
Area
Access
Upper Data Bus Lower Data Bus
Size Read/Write Address Valid Strobe (D15 to D8)
(D7 to D0)
8-bit
Byte Read
—
access
area
Write
—
RD
HWR
Valid
Invalid
Undetermined
data
16-bit
access
area
Byte Read
Write
Even
Odd
Even
RD
HWR
Valid
Invalid
Valid
Invalid
Valid
Undetermined
data
Odd
LWR
Undetermined
data
Valid
Word Read
—
RD
Valid
Valid
Write
—
HWR, LWR Valid
Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4 Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width
is selected according to the operating mode. The bus specifications described here cover basic
items only, and the following sections should be referred to for further details: section 6.4, Basic
Bus Interface, section 6.5, DRAM Interface, section 6.8, Burst ROM Interface.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS₀ signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space.
When area 1 and 6 external space is accessed, the CS₁ and CS₆ pin signals respectively can be
output.
Only the basic bus interface can be used for areas 1 and 6.
The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Rev. 2.00, 09/03, page 139 of 890