HD64F3028F25 Datasheet, PDF(72/925 Page) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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HD64F3028F25 Datasheet, PDF (72/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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Execution of BCLR Instruction

BCLR #0, @P4DDR ;Clear bit 0 in data direction register

After Execution of BCLR Instruction

Input/output

DDR

P47

Output

1

P46

Output

1

P45

Output

1

P44

Output

1

P43

Output

1

P42

Output

1

P41

Output

1

P40

Input

0

Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since

P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.

As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR

are set to 1, making P47 and P46 output pins.

The BCLR instruction can be used to clear flags in the on-chip registers to 0. In an interrupt-

handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the

flag ahead of time.

Rev. 2.00, 09/03, page 40 of 890

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