HD64F3028F25 Datasheet, PDF (153/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE
0
1
Description
WAIT pin wait input is disabled, and the WAIT pin can be used as an
input/output port
(Initial value)
WAIT pin wait input is enabled
6.2.6 Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(CS₇ to CS₄).
If output of a chip select signal is enabled by a setting in this register, the corresponding pin
functions as a chip select signal (CS₇ to CS₄) output regardless of any other settings. CSCR
cannot be modified in single-chip mode.
Bit
7
6
5
4
3
2
1
0
CS7E CS6E CS5E CS4E
—
—
—
—
Initial value
0
0
0
0
1
1
1
1
Read/Write R/W
R/W
R/W
R/W
—
—
—
—
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Reserved bits
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE
0
1
Note: n = 7 to 4
Description
Output of chip select signal CSn is disabled
Output of chip select signal CSn is enabled
(Initial value)
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev. 2.00, 09/03, page 121 of 890