HD64F3028F25 Datasheet, PDF (106/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

φ
RES
Address bus
RD
HWR, LWR
D₁₅ to D₀
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1)
(3)
(5)
High
(2)
(4)
(6)
(1), (3)
(2), (4)
(5)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset exception handling vector address)
Start address
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Figure 4.3 Reset Sequence (Modes 2 and 4)
Rev. 2.00, 09/03, page 74 of 890